FPGA-based biophysically-meaningful modeling of olivocerebellar neurons
Paper i proceeding, 2014

The Inferior-Olivary nucleus (ION) is a well-charted region of the brain, heavily associated with sensorimotor control of the body. It comprises ION cells with unique properties which facilitate sensory processing and motor-learning skills. Various simulation models of ION-cell networks have been written in an attempt to unravel their mysteries. However, simulations become rapidly intractable when biophysically plausible models and meaningful network sizes (100 cells) are modeled. To overcome this problem, in this work we port a highly detailed ION cell network model, originally coded in Matlab, onto an FPGA chip. It was first converted to ANSI C code and extensively profiled. It was, then, translated to HLS C code for the Xilinx Vivado toolflow and various algorithmic and arithmetic optimizations were applied. The design was implemented in a Virtex 7 (XC7VX485T) device and can simulate a 96-cell network at real-time speed, yielding a speedup of 700 compared to the original Matlab code and 12.5 compared to the reference C implementation running on a Intel Xeon 2.66GHz machine with 20GB RAM. For a 1,056-cell network (non-real-time), an FPGA speedup of 45 against the C code can be achieved, demonstrating the design's usefulness in accelerating neuroscience research. Limited by the available on-chip memory, the FPGA can maximally support a 14,400-cell network (non-real-time) with online parameter configurability for cell state and network size. The maximum throughput of the FPGA IONnetwork accelerator can reach 2.13 GFLOPS.

Spiking Neural Networks

Computational Neuroscience


Inferior Olive

Hodgkin Huxley


G. Smaragdos

Erasmus University Medical Center

S. Isaza

Universidad de Antioquia

M. Van Eijk

Technische Universiteit Delft

Ioannis Sourdis

Chalmers, Data- och informationsteknik, Datorteknik

C. Strydis

Erasmus University Medical Center

2014 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2014; Monterey, CA; United States; 26 February 2014 through 28 February 2014