Modeling Energy-Performance Tradeoffs in ARM big. LITTLE Architectures
Paper i proceeding, 2017

Heterogeneous multicores provide alternative core types and potentially multiple voltage-frequency levels to execute workloads more efficiently. One fundamental obstacle for capitalizing their potential performance and energy gains is identifying the most appropriate configuration (core type and voltage-frequency pair) for executing the computations at hand. In this paper, we analyze an ARM big. LITTLE architecture and show that the most efficient configuration is not always the expected one. We study the performance and energy tradeoffs of the big and the LITTLE ARM cores at different voltage and frequency levels. To do so we use various workloads and observe the overheads and benefits from using one configuration over another. Subsequently, we investigate how the workload characteristics and their execution on a particular core type affect energy consumption. We develop a lightweight energy model, suitable for runtime use, to accurately capture the above tradeoffs. Our model uses as input parameters only the instructions per cycle (IPC) and instruction mix. We evaluate the accuracy of the model across the two core types, different frequencies and various benchmarks. The model is able to predict the changes in the energy consumption of a program when moving from one configuration to another with an average error of 4.7%. Moreover, it is able to sort correctly 96% of the configurations across all benchmarks based on their energy consumption. Finally, our energy model can predict correctly for 22 out of 26 benchmarks the configuration that minimizes the energy-delay product (EDP); in the remaining four benchmarks the increase in EDP is less than 2.46%.


Evangelos Vasilakis

Chalmers, Data- och informationsteknik, Datorteknik

Ioannis Sourdis

Chalmers, Data- och informationsteknik, Datorteknik

Vassilis Papaefstathiou

Idryma Technologias kai Erevnas (FORTH)

Antonis Psathakis

Idryma Technologias kai Erevnas (FORTH)

Manolis G. H. Katevenis

Idryma Technologias kai Erevnas (FORTH)

International Symposium on Power and Timing Modeling Optimization and Simulation

2474-5456 (ISSN)

978-1-5090-6462-5 (ISBN)

27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Thessaloniki, Greece,



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