Reconfigurable Acceleration and Dynamic Partial Self-Reconfiguration in General Purpose Computing
Paper i proceeding, 2011

In this paper, we describe a generic approach for integrating a dynamically reconfigurable device into a general purpose system interconnected with a high-speed link. The system can dynamically install and execute hardware instances of functions to accelerate parts of a given software code. The hardware descriptions of the functions (bitstreams) are inserted into the executable binary running on the system. Our compiler further inserts system-calls to the software code to control the reconfigurable device. Thereby, the general purpose host-processor of the system manages the hardware reconfiguration and execution through a Linux device driver. The device has direct access to the main memory (DMA) operating in the virtual address space; it further supports memory mapped IO for data and control, and is able to raise and handle interrupts for synchronization. The above system is implemented on a general purpose machine providing a HyperTransport bus to connect a Xilinx Virtex4-100 FPGA, an AMD Opteron-244, and 1 GB of DDR main memory. We evaluate our proposal using a secure audio processing application. We accelerate in hardware the Audio processing kernel as well as the subsequent AES encryption function via dynamic partial self-reconfiguration. The proposed system achieves a 12 speedup over a software for the application at hand.


Ioannis Sourdis

Chalmers, Data- och informationsteknik, Datorteknik

Abhijit Nandy

TU Delft

Venkatasubramanian Viswanathan

TU Delft

Anthony Brandon

TU Delft

D. Theodoropoulos

TU Delft

Georgi Gaydadjiev

Chalmers, Data- och informationsteknik, Datorteknik

2011 International Conference on Field-Programmable Technology, FPT 2011; New Delhi; India; 12 December 2011 through 14 December 2011

978-145771740-6 (ISBN)




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