Hybrid2: Combining Caching and Migration in Hybrid Memory Systems
Paper in proceeding, 2020

This paper considers a hybrid memory system composed of memory technologies with different characteristics; in particular a small, near memory exhibiting high bandwidth, i.e., 3D-stacked DRAM, and a larger, far memory offering capacity at lower bandwidth, i.e., off-chip DRAM. In the past,
the near memory of such a system has been used either as a DRAM cache or as part of a flat address space combined with a migration mechanism.
Caches and migration offer different tradeoffs (between performance, main memory capacity, data transfer costs, etc.) and share similar challenges related to
data-transfer granularity and metadata management.
This paper proposes Hybrid2 , a new hybrid memory system architecture that combines a DRAM cache with a migration scheme. Hybrid 2 does not deny valuable capacity from the memory system because it uses only a small fraction of the near memory as a DRAM cache; 64MB in our experiments.
It further leverages the DRAM cache as a staging area to select the data most suitable for migration.
Finally, Hybrid2 alleviates the metadata overheads of both DRAM caches and migration using a common mechanism.
Using near to far memory ratios of 1:16, 1:8 and 1:4 in our experiments, Hybrid2 on average outperforms current state-of-the-art migration schemes by 7.9%, 9.1% and 6.4%, respectively.
In the same system configurations, compared to DRAM caches Hybrid2 gives away on average only 0.3%, 1.2%, and 5.3% of performance offering 5.9%, 12.1%, and 24.6% more main memory capacity, respectively.

Hybrid Memory Systems

Data Migration

DRAM caches


Evangelos Vasilakis

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Vasileios Papaefstathiou

Foundation for Research and Technology Hellas (FORTH)

Pedro Petersen Moura Trancoso

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Ioannis Sourdis

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings - International Symposium on High-Performance Computer Architecture

15300897 (ISSN)

649-662 9065506
978-172816149-5 (ISBN)

26th IEEE International Symposium on High Performance Computer Architecture, HPCA 2020
San Diego, USA,

Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)

European Commission (EC) (EC/H2020/671632), 2015-10-01 -- 2018-12-31.

Subject Categories

Computer Engineering

Embedded Systems

Computer Systems

Areas of Advance

Information and Communication Technology


C3SE (Chalmers Centre for Computational Science and Engineering)



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