Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints
Paper in proceeding, 2020
Performance and energy modeling
Dynamic voltage-frequency scaling
Resource management
Reconfigurable architectures
Memory level parallelism
Multicore processor
Quality of service
Cache partitioning
Author
Mehrzad Nejat
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Madhavan Manivannan
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Miquel Pericas
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Per Stenström
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020
590-601 9139837
New Orleans, USA,
Subject Categories
Computer Engineering
Embedded Systems
Computer Systems
Driving Forces
Sustainable development
DOI
10.1109/IPDPS47924.2020.00067