Madhavan Manivannan

Research Engineer at Computer Engineering (Chalmers)

Source: chalmers.se

Contact Details

Publications (26)
Projects (0)

Showing 26 publications

2022

Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack between QoS-Constrained Applications

Mehrzad Nejat, Madhavan Manivannan, Miquel Pericas et al

Transactions on Architecture and Code Optimization. Vol. 19 (2)

Journal article

2022

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures

Jing Chen, Madhavan Manivannan, Bhavishya Goel et al

Proceedings - Symposium on Computer Architecture and High Performance Computing, p. 326-335

Paper in proceeding

Show project

2022

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes

Jing Chen, Madhavan Manivannan, Mustafa Abduljabbar et al

Transactions on Architecture and Code Optimization. Vol. 19 (2)

Journal article

Show project

2021

CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling

Nadja Holtryd, Madhavan Manivannan, Per Stenström et al

30th International Conference on Parallel Architectures and Compilation Techniques (Proceedings), p. 213-225

Paper in proceeding

2020

DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors

Nadja Holtryd, Madhavan Manivannan, Per Stenström et al

Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020, p. 578-589

Paper in proceeding

Show project

2020

Scheduling Task-parallel Applications in Dynamically Asymmetric Environments

Jing Chen, Pirah Noor Soomro, Mustafa Abduljabbar et al

ACM International Conference Proceeding Series

Paper in proceeding

Show project

2020

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing

B. Salami, K. Parasyris, A. Cristal et al

PROCEEDINGS OF THE 2020 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2020), p. 169-174

Paper in proceeding

2020

Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading

Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericas et al

Proceedings of the 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, p. 967-970

Paper in proceeding

2020

Enhancing thread-level parallelism in asymmetric multicores using transparent instruction offloading

Jeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericas et al

Proceedings - Design Automation Conference. Vol. 2020-July

Paper in proceeding

2020

Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints

Mehrzad Nejat, Madhavan Manivannan, Miquel Pericas et al

Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium, IPDPS 2020, p. 590-601

Paper in proceeding

2020

Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems

Mehrzad Nejat, Madhavan Manivannan, Miquel Pericas et al

Journal of Parallel and Distributed Computing. Vol. 144, p. 246-259

Journal article

2018

Global dead-block management for task-parallel programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al

Transactions on Architecture and Code Optimization. Vol. 15 (3)

Journal article

2017

Runtime-Assisted Global Cache Management for Task-based Parallel Programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al

IEEE Computer Architecture Letters. Vol. 16 (2), p. 145-148

Journal article

Show project

2016

Towards Runtime-Assisted Cache Management for Task-Parallel Programs

Madhavan Manivannan

Doctoral thesis

2016

A Case for Runtime-Assisted Global Cache Management

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al

Report

2016

RADAR: Run-time assisted Dead-Region Management for Last-Level Caches

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al

IEEE International Symposium on High Performance Computer Architecture, p. 11-

Paper in proceeding

2016

RADAR: Runtime-assisted dead region management for last-level caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al

22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, 12-16 March 2016, p. 644-656

Paper in proceeding

2015

RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al

Report

2014

Runtime-guided cache coherence optimizations in multi-core architectures

Madhavan Manivannan, Per Stenström

Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, p. 625-636

Paper in proceeding

2013

Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures

Madhavan Manivannan, Per Stenström

Report

2013

Analysis and Optimization of Communication Overheads in Multi-core Architectures

Madhavan Manivannan

Licentiate thesis

2013

Efficient Forwarding of Producer-Consumer Data in Task-based Programs

Madhavan Manivannan, Anurag Negi, Per Stenström

Report

2013

Efficient Forwarding of Producer-Consumer Data in Task-based Programs

Madhavan Manivannan, Anurag Negi, Per Stenström

Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2013, Lyon, 1-4 October 2013, p. 517-522

Paper in proceeding

2011

Implications of Merging Phases on Scalability of Multicore Architectures

Madhavan Manivannan, Ben Juurlink, Per Stenström

Internantional Conference on Supercomputing (ICS), p. Page 380-

Conference poster

2011

Implications of Merging Phases on Scalability of Multi-core Architectures

Madhavan Manivannan, Ben Juurlink, Per Stenström

Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011, p. 622-631

Paper in proceeding

2010

Implications of Serial Reduction Phases in Data Mining Applications on Scalability of Multi-core Designs

Madhavan Manivannan, Per Stenström

Proceedings of the Third Swedish Workshop on Multicore Computing

Other conference contribution

Download publication list

You can download this list to your computer.

Filter and download publication list

As logged in user (Chalmers employee) you find more export functions in MyResearch.

You may also import these directly to Zotero or Mendeley by using a browser plugin. These are found herer:

Zotero Connector
Mendeley Web Importer

The service SwePub offers export of contents from Research in other formats, such as Harvard and Oxford in .RIS, BibTex and RefWorks format.

There are no projects.

There might be more projects where Madhavan Manivannan participates, but you have to be logged in as a Chalmers employee to see them.