STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures
Paper in proceeding, 2022

Reducing the energy consumption of parallel applications is becoming increasingly important. Current chip multiprocessors (CMPs) incorporate asymmetric cores (i.e. static asymmetry) and DVFS (i.e. dynamic asymmetry) to enable energy efficient execution. To reduce cost and complexity, designs typically organize asymmetric cores into core-clusters supporting the same DVFS setting across cores in a cluster. Recent approaches that focus on energy efficient scheduling of task-based parallel applications predominantly rely on dynamic asymmetry, particularly per-core DVFS, for reducing energy. More importantly, they do not consider the impact of task heterogeneity (i.e. varying task characteristics, intra-task parallelism and task granularity) in conjunction with the dynamic and static asymmetries provided by the platform. Together, these provide significant opportunities for further energy savings. In this work we propose STEER, a framework that enables energy efficient execution of task-based parallel applications by leveraging static asymmetry, dynamic asymmetry and task heterogeneity. STEER utilizes a combination of models and heuristics to predict the execution time and power consumption and determine core type, number of cores and frequency for running tasks. Our evaluation shows that STEER achieves 38% energy reduction on average compared to the state-of-the-art approaches.

Resource management

Runtimes

Energy

Task scheduling

DVFS

Power modeling

Performance modeling

Author

Jing Chen

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Madhavan Manivannan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Bhavishya Goel

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Mustafa Abduljabbar

Chalmers, Physics, E-commons

Ohio State University

Miquel Pericas

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Proceedings - Symposium on Computer Architecture and High Performance Computing

15506533 (ISSN)

326-335
9781665451550 (ISBN)

34th IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2022
Bordeaux, France,

European, extendable, energy-efficient, energetic, embedded, extensible, Processor Ecosystem (eProcessor)

European Commission (EC) (EC/H2020/956702), 2021-01-01 -- 2024-06-30.

Subject Categories

Computer Engineering

Embedded Systems

Computer Systems

DOI

10.1109/SBAC-PAD55451.2022.00043

More information

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1/3/2024 9