Madhavan Manivannan

Doktor vid Chalmers, Data- och informationsteknik, Datorteknik

Visar 15 publikationer

2018

Global dead-block management for task-parallel programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
Transactions on Architecture and Code Optimization. Vol. 15 (3)
Artikel i vetenskaplig tidskrift
2017

Runtime-Assisted Global Cache Management for Task-based Parallel Programs

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
IEEE Computer Architecture Letters. Vol. 16 (2), p. 145-148
Artikel i vetenskaplig tidskrift
2016

A Case for Runtime-Assisted Global Cache Management

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
Rapport
2016

RADAR: Run-time assisted Dead-Region Management for Last-Level Caches

Madhavan Manivannan, Miquel Pericas, Vasileios Papaefstathiou et al
IEEE International Symposium on High Performance Computer Architecture, p. 11-
Paper i proceeding
2016

RADAR: Runtime-assisted dead region management for last-level caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al
22nd IEEE International Symposium on High Performance Computer Architecture, HPCA 2016, Barcelona, Spain, 12-16 March 2016, p. 644-656
Paper i proceeding
2015

RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches

Madhavan Manivannan, Vasileios Papaefstathiou, Miquel Pericas et al
Rapport
2014

Runtime-guided cache coherence optimizations in multi-core architectures

Madhavan Manivannan, Per Stenström
Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS, p. 625-636
Paper i proceeding
2013

Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures

Madhavan Manivannan, Per Stenström
Rapport
2013

Efficient Forwarding of Producer-Consumer Data in Task-based Programs

Madhavan Manivannan, Anurag Negi, Per Stenström
Rapport
2013

Efficient Forwarding of Producer-Consumer Data in Task-based Programs

Madhavan Manivannan, Anurag Negi, Per Stenström
Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2013, Lyon, 1-4 October 2013, p. 517-522
Paper i proceeding
2011

Implications of Merging Phases on Scalability of Multicore Architectures

Madhavan Manivannan, Ben Juurlink, Per Stenström
Internantional Conference on Supercomputing (ICS), p. Page 380-
Poster (konferens)
2011

Implications of Merging Phases on Scalability of Multi-core Architectures

Madhavan Manivannan, Ben Juurlink, Per Stenström
Proceedings of the International Conference on Parallel Processing. 40th International Conference on Parallel Processing, ICPP 2011, Taipei City, 13-16 September 2011, p. 622-631
Paper i proceeding
2010

Implications of Serial Reduction Phases in Data Mining Applications on Scalability of Multi-core Designs

Madhavan Manivannan, Per Stenström
Proceedings of the Third Swedish Workshop on Multicore Computing
Konferensbidrag (offentliggjort, men ej förlagsutgivet)

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