Madhavan Manivannan
Visar 32 publikationer
SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs
JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency
SoK: Analysis of Root Causes and Defense Strategies for Attacks on Microarchitectural Optimizations
eProcessor: European, Extendable, Energy-Efficient, Extreme-Scale, Extensible, Processor Ecosystem
SCALE: Secure and Scalable Cache Partitioning
STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures
ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes
CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling
Enhancing thread-level parallelism in asymmetric multicores using transparent instruction offloading
LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing
DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors
Scheduling Task-parallel Applications in Dynamically Asymmetric Environments
Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading
Global dead-block management for task-parallel programs
Runtime-Assisted Global Cache Management for Task-based Parallel Programs
RADAR: Runtime-assisted dead region management for last-level caches
Towards Runtime-Assisted Cache Management for Task-Parallel Programs
RADAR: Run-time assisted Dead-Region Management for Last-Level Caches
A Case for Runtime-Assisted Global Cache Management
RADAR: Runtime-Assisted Dead Region Management for Last-Level Caches
Runtime-guided cache coherence optimizations in multi-core architectures
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Analysis and Optimization of Communication Overheads in Multi-core Architectures
Runtime-Guided Cache Coherence Optimizations in Multi-core Architectures
Efficient Forwarding of Producer-Consumer Data in Task-based Programs
Implications of Merging Phases on Scalability of Multi-core Architectures
Implications of Merging Phases on Scalability of Multicore Architectures
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