CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling
Paper in proceeding, 2021

Reducing the average memory access time is crucial for improving the performance of applications running on multicore architectures. With workload consolidation this becomes increasingly challenging due to shared resource contention. Techniques for partitioning of shared resources - cache and bandwidth - and prefetch throttling have been proposed to mitigate contention and reduce the average memory access time. However, existing proposals only employ a single or a subset of these techniques and are therefore not able to exploit the full potential of coordinated management of cache, bandwidth and prefetching. Our characterization results show that application performance, in several cases, is sensitive to prefetching, cache and bandwidth allocation altogether. Furthermore, the results show that managing these together provides higher performance potential during workload consolidation as it enables more resource trade-offs. In this paper, we propose CBP a coordination mechanism for dynamically managing prefetching throttling, cache and bandwidth partitioning, in order to reduce average memory access time and improve performance. CBP works by employing individual resource managers to determine the appropriate setting for each resource and a coordinating mechanism in order to enable inter-resource trade-offs. Our evaluation on a 16-core CMP shows that CBP, on average, improves performance by 11% compared to the state-of-the-art technique that manages cache partitioning and prefetching and by 50% compared to the baseline without cache partitioning, bandwidth partitioning and prefetch throttling.

Cache partitioning, prefetching, bandwidth partitioning

Author

Nadja Holtryd

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Madhavan Manivannan

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Per Stenström

Computer and Network Systems

Miquel Pericas

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

1089795X (ISSN)

Vol. 2021-September 213-225
9781665442787 (ISBN)

30th International Conference on Parallel Architectures and Compilation Techniques (PACT)
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Subject Categories

Computer Systems

DOI

10.1109/PACT52795.2021.00023

More information

Latest update

7/17/2024