Dual Data Rate Network-on-Chip Architectures
Doctoral thesis, 2021
Chalmers, Computer Science and Engineering (Chalmers)
FastTrackNoC: A NoC with FastTrack Router Datapaths
HighwayNoC: Approaching Ideal NoC Performance With Dual Data Rate Routers
IEEE/ACM Transactions on Networking,; Vol. 29(2021)p. 318-331
FreewayNoC: A DDR NoC with Pipeline Bypassing
2018 12th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018,; (2018)
Paper in proceeding
DDRNoC: Dual Data-Rate Network-on-Chip
Transactions on Architecture and Code Optimization,; Vol. 15(2018)
Over the years, the number of processing cores in a CPU chip has increased from two to four to over a thousand in some cutting-edge CPUs today. A CPU with so many cores can offer very high performance, but it is limited by, among others, the inefficient communication between the cores in a multi-core chip. A high-speed communication fabric is then deployed within the chip to connect all the cores in an efficient way and improve CPU performance. This thesis proposes novel architectures for this on-chip interconnect which offer better performance compared to existing approaches.
Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)
European Commission (EC) (EC/H2020/671632), 2015-10-01 -- 2018-12-31.
Green Computing Node for European micro-servers (EUROSERVER)
European Commission (EC) (EC/FP7/610456), 2013-09-01 -- 2016-08-31.
Areas of Advance
Information and Communication Technology
C3SE (Chalmers Centre for Computational Science and Engineering)
Innovation and entrepreneurship
Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 4964
Opponent: Tushar Krishna, Georgia Institute of Technology, USA