Building Verified Hardware and Verified Stacks in HOL
Doctoral thesis, 2021
This thesis explores building provably correct software and hardware inside the HOL4 interactive theorem prover. Interactive theorem provers such as HOL4 are proof environments where manual (human) and automated (machine) proofs can be composed in logically safe ways and all proof steps (be it manual or automated) are mechanically checked.
In this thesis, we are in particular interested in systems consisting of both software and hardware, such as so-called verified stacks. A verified stack is a computer system accompanied by a correctness theorem ensuring the correctness of its running software down to the computer system's hardware implementation.
One contribution of this thesis is that we provide new tools to build verified stacks. Specifically, we provide a new proof-producing Verilog code generator capable of translating hardware circuits proved correct inside HOL4 to the hardware description language Verilog. We also provide a verified Verilog synthesis tool, called Lutsig, for (a class of) FPGAs. Lutsig translates Verilog designs, such as those generated by our proof-producing Verilog code generator, to technology-mapped netlists. With the combined help of the Verilog code generator and Lutsig, it is possible for hardware designers to design and prove circuits correct inside HOL4 and then translate their circuits down to the netlist level while simultaneously carrying along proved properties.
Another contribution is that we apply the new tools in concrete case studies. In particular, one of our case studies contributes to the tradition of building verified stacks as follows. In the case study, we use our Verilog code generator in the construction of a verified proof-of-concept processor that we synthesize for an FPGA board. Building upon this work, we use the processor as the hardware basis for verified stacks based on CakeML programs, including a stack for compiling CakeML programs and a stack for checking proofs. To be able to construct such stacks, we adapt and extend the verified CakeML compiler and its development methodology to support targeting the new processor we have constructed. The CakeML compiler previously only supported compilation to x86, ARM and other architectures without verified implementations.
In this thesis, we are in particular interested in systems consisting of both software and hardware, such as so-called verified stacks. A verified stack is a computer system accompanied by a correctness theorem ensuring the correctness of its running software down to the computer system's hardware implementation.
One contribution of this thesis is that we provide new tools to build verified stacks. Specifically, we provide a new proof-producing Verilog code generator capable of translating hardware circuits proved correct inside HOL4 to the hardware description language Verilog. We also provide a verified Verilog synthesis tool, called Lutsig, for (a class of) FPGAs. Lutsig translates Verilog designs, such as those generated by our proof-producing Verilog code generator, to technology-mapped netlists. With the combined help of the Verilog code generator and Lutsig, it is possible for hardware designers to design and prove circuits correct inside HOL4 and then translate their circuits down to the netlist level while simultaneously carrying along proved properties.
Another contribution is that we apply the new tools in concrete case studies. In particular, one of our case studies contributes to the tradition of building verified stacks as follows. In the case study, we use our Verilog code generator in the construction of a verified proof-of-concept processor that we synthesize for an FPGA board. Building upon this work, we use the processor as the hardware basis for verified stacks based on CakeML programs, including a stack for compiling CakeML programs and a stack for checking proofs. To be able to construct such stacks, we adapt and extend the verified CakeML compiler and its development methodology to support targeting the new processor we have constructed. The CakeML compiler previously only supported compilation to x86, ARM and other architectures without verified implementations.
hardware synthesis
compilers
formal verification
interactive theorem proving
Online (contact Andreas for the Zoom room password)
Opponent: Prof. Warren A. Hunt, Jr., University of Texas at Austin, United States
Author
Andreas Lööw
Chalmers, Computer Science and Engineering (Chalmers), Formal methods
Verified Compilation on a Verified Processor
PROCEEDINGS OF THE 40TH ACM SIGPLAN CONFERENCE ON PROGRAMMING LANGUAGE DESIGN AND IMPLEMENTATION (PLDI '19),;(2019)p. 1041-1053
Paper in proceeding
A Proof-Producing Translator for Verilog Development in HOL
Proceedings - 2019 IEEE/ACM 7th International Workshop on Formal Methods in Software Engineering, FormaliSE 2019,;(2019)p. 99-108
Paper in proceeding
Lutsig: A Verified Verilog Compiler for Verified Circuit Development
Proceedings of the 10th ACM SIGPLAN International Conference on Certified Programs and Proofs,;(2021)p. 46-60
Paper in proceeding
Andreas Lööw, Lutsig 2.0: Verilog, Synthesis-Tool Verification, and Circuit-Verification Methodology
För att de datorsystem vi använder i dag, så som mobiltelefoner och bärbara datorer, ska fungera som de är tänkta att fungera är det viktigt att alla mjukvaru- och hårdvarukomponenter som systemen består utav är korrekta. I denna avhandling visar vi hur det med hjälp av interaktiv bevisföring går att etablera korrektheten hos system som består utav både mjukvara och hårdvara. Interaktiv bevisföring är en typ av matematik där människor och datorer samarbetar för att tillsammans konstruera matematiska bevis. Interaktiv bevisföring heter på engelska interactive theorem proving, och de bevisprogram som kan samarbeta med människor kallas för proof assistants (d.v.s., bevisassistenter).
I denna avhandling så visar vi hur vi har byggt konkreta datorsystem, som kan utföra uppgifter så som att kompilera mjukvaruprogram och kontrollera matematiska bevis, och vi visar hur korrektheten hos dessa system kan etableras med hjälp av interaktiv bevisföring. Vidare introducerar vi nya verktyg som kan användas i hårdvaruutveckling baserad på interaktiv bevisföring. Gemensamt för dessa verktyg är att de använder sig av det mycket använda hårdvaruspråket Verilog, vilket förenklar för personer som från tidigare är bekanta med hårdvaruutveckling att förstå sig på våra nya verktyg.
I denna avhandling så visar vi hur vi har byggt konkreta datorsystem, som kan utföra uppgifter så som att kompilera mjukvaruprogram och kontrollera matematiska bevis, och vi visar hur korrektheten hos dessa system kan etableras med hjälp av interaktiv bevisföring. Vidare introducerar vi nya verktyg som kan användas i hårdvaruutveckling baserad på interaktiv bevisföring. Gemensamt för dessa verktyg är att de använder sig av det mycket använda hårdvaruspråket Verilog, vilket förenklar för personer som från tidigare är bekanta med hårdvaruutveckling att förstå sig på våra nya verktyg.
Subject Categories
Computer and Information Science
ISBN
978-91-7905-518-9
Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 4985
Publisher
Chalmers
Online (contact Andreas for the Zoom room password)
Opponent: Prof. Warren A. Hunt, Jr., University of Texas at Austin, United States