Power Estimation and Multi-Phase Clock Generation for the Deep Submicron Era

Doctoral thesis, 2003

Scaling has been the driving force behind the immense development the field of electronics has seen over the last few decades. It has brought us from integrated circuits operating in the kilohertz range in the 1970s to the gigahertz range in just thirty years. Scaling has also brought the number of transistors on a single chip from a few thousand to hundreds of millions in the same time frame. Because of the development we have seen in the past, there are expectations for the field to continue developing at the same pace in the future. Modern high-performance integrated circuits have a power density that exceeds that of a hot plate. A methodology is presented which increases the accuracy of high-level power estimation which is a requirement for early design-space exploration. The methodology is an extension of traditional register transfer level power estimation methodologies but gains accuracy by being able to distinguish between different power dissipation mechanisms. It is becoming more and more difficult to increase the clock frequency for integrated circuits as scaling alone will not maintain the development seen in the past. New types of multi-phase clock generation delay-locked loops might prove to be one road to increased performance. A mixed-mode delay-locked loop architecture is proposed with the intent to retain the good properties from both analog and digital implementations. The most important property of the digital architecture that is made available in the mixed-mode architecture is the ability to operate in a clock-gated environment. An implementation of this mixed-mode architecture is also presented which preserves the simple delay elements from analog architectures while at the same time enabling clock gating which was previously reserved for digital architectures.