Daniel Eckerbert

Showing 8 publications


Toward Architecture-Based Test-Vector Generation for Timing Verification of Fast Parallel Multipliers

Henrik Eriksson, Per Larsson-Edefors, Daniel Eckerbert
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Journal article

A Power Cut-Off Technique for Gate Leakage Suppression

Mindaugas Drazdziulis, Per Larsson-Edefors, Daniel Eckerbert et al
European Solid-State Circuits Conference (ESSCIRC), p. 171-174
Paper in proceeding

A Deep Submicron Power Estimation Methodology Adaptable to Variations Between Power Characterization and Estimation

Daniel Eckerbert, Per Larsson-Edefors
Proceedings of Asia South-Pacific Design Automation Conference (ASPDAC), Kitakyushu, 21-24 January 2003, p. 716-719
Paper in proceeding

A Mixed-Mode Delay-Locked Loop Architecture

Daniel Eckerbert, Lars Svensson, Per Larsson-Edefors
Proceedings of the 21st International Conference on Computer Design (ICCD), San Jose, 13-15 October 2003, p. 261-263
Paper in proceeding

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects

Per Larsson-Edefors, Daniel Eckerbert, Henrik Eriksson et al
Proceedings of IEEE Computer Society Annual Symposium on VLSI
Paper in proceeding

Multi-Phase Clock Generation and Synchronization

Atila Alvandpour, Daniel Eckerbert, Ram K. Krishnamurthy

A 3.5GHz 32mW 150nm Multiphase Clock Generator for High-Performance Microprocessors

A. Alvandpour, R.K. Krishnamurthy, Daniel Eckerbert et al
Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 9-13 February 2003
Paper in proceeding

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