Low Power and High Linear, Low Noise Amplifier Designed in 22nm FDSOI Technology for 5G Wireless Systems
Paper in proceeding, 2023
The focus of this paper is to present a low-power and high-performance LNA design, implemented in 22nm FDSOI process for fifth generation (5G) communication systems. The LNA employs an inductively degenerated common source topology with a cascode device. At a frequency of 28GHz, the LNA achieves a gain of 12.4dB and an input-referred third-order intercept point (IIP3) of 2.4dBm. The LNA has a 3-dB bandwidth of 14GHz, a minimum noise figure (NF) of 2.2dB at 28GHz, and a power dissipation (PDC) of 7.2mW.
22-nm CMOS
FD-SOI
millimeter-wave integrated circuits
low noise amplifiers (LNAs)
Author
Marzieh Mollaalipouramiri
Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics
Koen Buisman
University of Surrey
Christian Fager
Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics
Herbert Zirath
Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics
Asia-Pacific Microwave Conference Proceedings, APMC
778-780
9781665494182 (ISBN)
31st Asia-Pacific Microwave Conference, APMC 2023
Taipei, Taiwan,
Taipei, Taiwan,
Subject Categories
Other Electrical Engineering, Electronic Engineering, Information Engineering
DOI
10.1109/APMC57107.2023.10439888