Benchmarking and Metrology of Scaled Superconducting Quantum Processors

Doctoral thesis, 2024

The field of computation, particularly the development of the modern computer, has seen tremendous growth in sophistication over the last century. The term "computer," which once referred to a job title a little more than half a century ago, now represents complex machinery capable of a myriad of tasks—ranging from the crucial management of global supply chain logistics to the mundane generation of an infinite supply of AI-generated cat pictures.

Quantum computing is often viewed as one of the next frontiers in information science, computing, and physics. However, it is not immediately evident that a computer based on quantum mechanics should even work. Noise in quantum systems hinders the direct implementation of many quantum algorithms. Achieving universal quantum computing necessitates the development of a fault-tolerant quantum computer, which requires thousands of physical qubits working together. This thesis explores whether our architecture can overcome these challenges and scale to such system sizes.

We begin by explaining the physics of superconducting transmon qubits and their control, starting with single-qubit operations. Next, we discuss qubit state measurement and how readout techniques can be enhanced using the transmon's multilevel nature. The primary focus, however, is on two- and multi-qubit operations. Our architecture utilizes fixed-frequency qubits with tunable couplers, which can be modulated via radio frequency to enable interactions between adjacent qubits. These interactions facilitate two-body couplings or simultaneous multi-qubit interactions, expanding our device's capabilities without requiring architectural changes.

We then describe the characterization techniques used to bring a device into specification for implementing a quantum algorithm. We explore advanced metrology techniques, such as tomography, to gain a more detailed understanding of the performance of specific logical operations.

With the control and characterization of the device established, we still need to develop techniques to assess how well our devices are performing. Benchmarking techniques allow us to compare the performance of our hardware against others in the quantum computing community. Standard techniques, such as coherence measurements, enable comparisons at the hardware level, while algorithmic benchmarks allow us to assess the effectiveness of our control.

Finally, we investigate whether the parametric architecture has any physical limitations when scaling to large system sizes. We identified a frequency allocation scheme for the qubits on our device, which holds the potential to scale to hundreds of qubits. While our current fabrication techniques would limit our device yield to 20% for 100 qubits, we find no intrinsic limitation to scaling beyond this. Improvements in our fabrication processes could increase both the yield of devices and the stability of designed parameters.