Benchmarking and Metrology of Scaled Superconducting Quantum Processors
Doktorsavhandling, 2024

The ultimate goal of quantum computing is to develop quantum algorithms and hardware that outperform any classical methods. However, noise in quantum systems hinders their direct implementation. Achieving universal quantum computing necessitates a fault-tolerant quantum computer, which requires thousands of physical qubits. This thesis explores whether our architecture can overcome these challenges and scale to the required number of qubits.

Superconducting quantum circuits are a highly developed platform for building quantum computers, leveraging advanced device design and fabrication technology that can scale rapidly to hundreds or thousands of qubits. Our architecture features fixed-frequency qubits connected by tunable couplers, operating at very low temperatures (∼10 mK). Qubits are controlled using radio-frequency electromagnetic fields, while magnetic fields parametrically modulate the couplers to enable interactions between qubits.

There are many axes along which one can scale to larger system sizes. The most commonly approached axis is by developing high-coherence quantum hardware. Coherence times determines the memory/operational lifetime of quantum information. Our fabrication has allowed us to achieve multi-qubit processors with coherence times over 100 µs. However, coherence times are not without a context, as we also require fast gate times. The control of quantum hardware is a second direction towards scaling; minimizing the time to implement a logical operation relative to the coherence times of the device. In our processors, we are able to implement two-qubit operations with < 1% error in 250 ns, with which we implemented two quantum algorithms to infer the performance of our architecture. Moreover we improve the readout accuracy in our architecture by artificially extending the lifetime of the qubit during measurement through a state shelving scheme.

A third, often overlooked axis for scaling quantum hardware is expanding the native logical gate set. Typically, quantum processors use a limited set of operations. We developed a technique to implement a native three-qubit gate by simultaneously applying our two-qubit operations, expanding the gate set without altering the architecture. This demonstrated coherence-limited performance and enabled faster generation of highly entangled states compared to using only two-qubit operations.

Although our parametric architecture offers advantages for scaling, significant challenges remain, particularly in maintaining coherence, minimizing crosstalk, and ensuring device yield as qubit numbers increase. This thesis explores the limitations and obstacles in scaling superconducting quantum processors, using experimental data and theoretical models. We address key issues with the parametric gate, such as frequency crowding and crosstalk, and discuss the fabrication tolerances needed to scale to a 100-qubit system.

benchmarking

metrology

parametric modulation

quantum information

circuit quantum electrodynamics

superconducting circuits

Kollektorn, MC2, Kemivägen 9, Chalmers
Opponent: Dr. Kevin Satzinger, Google Quantum AI, USA

Författare

Christopher Warren

Chalmers, Mikroteknologi och nanovetenskap, Kvantteknologi

Improved Success Probability with Greater Circuit Depth for the Quantum Approximate Optimization Algorithm

Physical Review Applied,;Vol. 14(2020)

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Fast Multiqubit Gates through Simultaneous Two-Qubit Gates

PRX Quantum,;Vol. 2(2021)

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Building blocks of a flip-chip integrated superconducting quantum processor

Quantum Science and Technology,;Vol. 7(2022)

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Extensive characterization and implementation of a family of three-qubit gates at the coherence limit

npj Quantum Information,;Vol. 9(2023)

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Reference-State Error Mitigation: A Strategy for High Accuracy Quantum Computation of Chemistry

Journal of Chemical Theory and Computation,;Vol. 19(2023)p. 783-789

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Mitigation of frequency collisions in superconducting quantum processors

Physical Review Research,;Vol. 5(2023)

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The field of computation, particularly the development of the modern computer, has seen tremendous growth in sophistication over the last century. The term "computer," which once referred to a job title a little more than half a century ago, now represents complex machinery capable of a myriad of tasks—ranging from the crucial management of global supply chain logistics to the mundane generation of an infinite supply of AI-generated cat pictures.

Quantum computing is often viewed as one of the next frontiers in information science, computing, and physics. However, it is not immediately evident that a computer based on quantum mechanics should even work. Noise in quantum systems hinders the direct implementation of many quantum algorithms. Achieving universal quantum computing necessitates the development of a fault-tolerant quantum computer, which requires thousands of physical qubits working together. This thesis explores whether our architecture can overcome these challenges and scale to such system sizes.

We begin by explaining the physics of superconducting transmon qubits and their control, starting with single-qubit operations. Next, we discuss qubit state measurement and how readout techniques can be enhanced using the transmon's multilevel nature. The primary focus, however, is on two- and multi-qubit operations. Our architecture utilizes fixed-frequency qubits with tunable couplers, which can be modulated via radio frequency to enable interactions between adjacent qubits. These interactions facilitate two-body couplings or simultaneous multi-qubit interactions, expanding our device's capabilities without requiring architectural changes.

We then describe the characterization techniques used to bring a device into specification for implementing a quantum algorithm. We explore advanced metrology techniques, such as tomography, to gain a more detailed understanding of the performance of specific logical operations.

With the control and characterization of the device established, we still need to develop techniques to assess how well our devices are performing. Benchmarking techniques allow us to compare the performance of our hardware against others in the quantum computing community. Standard techniques, such as coherence measurements, enable comparisons at the hardware level, while algorithmic benchmarks allow us to assess the effectiveness of our control.

Finally, we investigate whether the parametric architecture has any physical limitations when scaling to large system sizes. We identified a frequency allocation scheme for the qubits on our device, which holds the potential to scale to hundreds of qubits. While our current fabrication techniques would limit our device yield to 20% for 100 qubits, we find no intrinsic limitation to scaling beyond this. Improvements in our fabrication processes could increase both the yield of devices and the stability of designed parameters.

An Open Superconducting Quantum Computer (OpenSuperQ)

Europeiska kommissionen (EU) (EC/H2020/820363), 2018-10-01 -- 2021-09-30.

Styrkeområden

Nanovetenskap och nanoteknik

Ämneskategorier

Subatomär fysik

Annan fysik

Nanoteknik

Den kondenserade materiens fysik

Fundament

Grundläggande vetenskaper

Infrastruktur

Nanotekniklaboratoriet

ISBN

978-91-8103-084-6

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 5542

Utgivare

Chalmers

Kollektorn, MC2, Kemivägen 9, Chalmers

Opponent: Dr. Kevin Satzinger, Google Quantum AI, USA

Mer information

Senast uppdaterat

2024-08-19