Flip-chip Integrated Superconducting Quantum Processors

Doctoral thesis, 2025

On the path toward fault-tolerant quantum computing—an endeavor motivated by the prospect of solving otherwise intractable computational problems in fields such as quantum chemistry, materials, and optimization—a key challenge is to scale up the number of quantum bits of information (qubits) a quantum computer can host while not degrading their performance. To this end, the superconducting quantum processor (SQP) has its advantages due to its flexible design, compatibility with microchip manufacturing processes, and addressability by microwaves generated by commercially available equipment.

This thesis is a demonstration of the scalability of SQPs. By adopting 3-dimensional integration technologies used in semiconductor manufacturing, flip-chip integrated SQPs can host dozens to hundreds of qubits, compared to the smaller number of qubits a single-chip architecture can accommodate. The first part of this thesis shows how we transferred the design of individual components of the SQP—qubits, couplers, readout resonators, and Purcell filters—into a flip-chip architecture while maintaining good qubit coherence and high control-and-measurement performance with additional fabrication processes. We pay special attention to the interchip spacing, an additional design parameter introduced in the flip-chip architecture, which has a large influence on the parameter predictability and performance of the SQP.

The second part of the thesis shows how we used these individual components to design a scaled-up SQP. The design workflow of a multi-qubit SQP, from parameter design to layout, is elaborated in detail. This workflow has resulted in a 25-qubit flip-chip integrated SQP, without degrading the qubit coherence and gate performance, further demonstrating the scalability of flip-chip integrated SQPs. We speed up this design workflow by introducing an analytic design method for superconducting resonators based on conformal mapping techniques, which we use to design readout resonators with parameters that are not affected by variations of the interchip spacing.