Reliable and Area-Efficient Polar Decoders for SRAM PUF-based Key Generation

Paper in proceeding, 2026

Physical unclonable functions (PUFs) offer several advantages for chip authentication, but their implementations must ensure reliable key generation while maintaining hardware efficiency. During key generation, error correction is required to suppress noise caused by environmental variations. Polar codes have emerged as a promising candidate, offering strong error-correction capability at short block lengths. However, their high decoding complexity is at odds with the constrained resources required by a PUF implementation. Sequential decoder architectures can mitigate this issue, however, storing log-likelihood ratios (LLRs) values still requires significant memory, especially when targeting a stringent block-error rate (BLER) of 10−9. To address this challenge, we propose two techniques: inline quantization eliminates the storage of input LLRs, while LLR operation fusion reduces the storage required for intermediate values. Synthesized in a 22-nm CMOS technology, our area-efficient polar decoders provide up to 29.4% memory usage reduction and 16.7% total area reduction over conventional decoders. These reductions enable area-efficient decoder implementations that meet stringent BLER requirements. For example, a P(1024, 64) decoder, occupying 4098μm2, tolerates a 0.18 input bit-error probability under a target BLER of 10−9.