Parameter Extraction and SPICE Modeling of Packaged GaN Power Transistors Using 2-port S-Parameter Characterization

Licentiate thesis, 2026

This thesis presents a standards-compatible characterization and modeling methodology for a commercial 650 V GaN transistor based on 2-port S-parameter measurements, targeting the accurate extraction of low-nanohenry inductances and picofarad-level capacitances. A systematic comparison with conventional one-port impedance techniques highlights 2-port S-parameters as a broadband and reliable approach for extracting small circuit elements in surface-mounted GaN devices.
To ensure accuracy and reliability in the low-value range, a dedicated short–open–load–thru (SOLT) calibration kit has been developed. The design incorporates a short-compensation structure that accounts for via and ground-plane inductance, enabling more reliable de-embedding of fixture residuals.
All measured impedance levels are constrained within the 10$\%$ accuracy range of the network analysis methods, ensuring traceable and reliable parameter extraction. The extracted parameters extend down to approximately 1 pF for capacitance, 157 pH for inductance, and 32 m$\Omega$ for resistance. The extracted inductances, resistances, and nonlinear capacitances are integrated into an industrially recognized physics-based SPICE compact model, establishing a practical workflow from device-level measurement to model implementation without requiring proprietary device information. Cross-domain validation in both frequency and time domains, including S-parameter verification up to 1 GHz and double-pulse test (DPT) up to 400 V, demonstrates close agreement between measurement and simulation in LTspice and Keysight ADS. At higher switching speeds, where parasitic effects dominate circuit behavior, the proposed model adequately predicts the measured ringing and switching waveform, whereas the supplier model exhibits noticeable deviations and excessive oscillations, highlighting the reliability and accuracy of the device parameter extraction. In addition, under identical simulation settings in LTspice and the same operation conditions, the proposed model demonstrates higher computational efficiency compared to the supplier’s model, making it suitable for practical circuit-level analysis with reduced simulation cost and improved transparency.