Emulation and Design of Polar Codes for PUF-based Key Generation

Paper in proceeding, 2026

Polar codes have gained increasing attention for physical unclonable function (PUF)-based key generation due to their strong error-correction performance at short block lengths and low hardware complexity when decoded using sequential successive cancellation (SC). However, reliable PUF-based key generation requires low block-error rates (BLERs) down to 10−12. Designing polar codes to satisfy such reliability requirements necessitates extensive evaluations. Additionally the inherently sequential nature of SC decoding leads to prohibitively long simulation runtimes. To address the runtime challenge, we propose a high-speed FPGA-based emulation platform featuring a deeply-pipelined and fully-unrolled FastSSC decoder which achieves a throughput of one codeword per cycle. With a 200-MHz clock, we can complete 1010 emulation runs in approximately 50 seconds and 1013 runs in about 14 hours. We perform comprehensive design space explorations to identify P(2048, 64) with 5-bit quantization as a code that satisfies the stringent reliability constraints of PUF-based key generation. The code achieves a BLER below 10−12 and 10−9 for an input bit-error probability of 0.15 and 0.25, respectively. In addition, we analyze the tradeoff between hardware complexity, the number of SRAM PUF source bits, and the maximum tolerable input bit-error probability under BLER requirements of 10−9 and 10−12, providing practical design guidelines for ASIC implementation.