Improved GaN-on-SiC transistor thermal resistance by systematic nucleation layer growth optimization
Paper in proceedings, 2013

Impressive power densities have been demonstrated for GaN-on-SiC based high-power high-frequency transistors, although further gains can be achieved by further minimizing the device thermal resistance. A significant 10-30% contribution to the total device thermal resistance originates from the high defect density AlN nucleation layer at the GaN/SiC interface. This thermal resistance contribution was successfully reduced by performing systematic growth optimization, investigating growth parameters including: Substrate pretreatment temperature, growth temperature and deposition time. Interfacial thermal resistance, characterized by time resolved Raman thermography measurements AlGaN/GaN HEMT structures, were minimized by using a substrate pretreatment and growth temperature of 1200 °C. Reducing the AlN thickness from 105 nm (3.3×10-8 W/m2K) to 35 nm (3.3×10-8 W/m2K), led to a ~2.5× interfacial thermal resistance reduction and the lowest value reported for a standard AlGaN/GaN HEMT structure.

Author

J. Pomeroy

University of Bristol

Niklas Rorsman

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

J. T. Chen

Linköping University

Urban Forsberg

Linköping University

E. Janzen

Linköping University

M. Kuball

University of Bristol

Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC

1550-8781 (ISSN)

Subject Categories

Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/CSICS.2013.6659233

ISBN

978-147990583-6

More information

Latest update

3/2/2018 6