Process optimization for SiGe pMOSFETs using low temperature oxides on ultra-thin cap layers
Paper in proceedings, 2004

We optimized the oxidation and annealing processes for SiGe quantum-well (QW) p-channel Metal-Oxide-Semiconductor Field-Effect Transistors (pMOSFETs) to maintain the strain in the channel and to suppress or eliminate the Si cap layer parasitic conduction. We fabricated and investigated poly-Si gated MOS capacitors incorporating 2nm low-temperature furnace oxides and optimized ultra-thin Si-cap layers. For these structures, we found that a rapid thermal annealing (RTA) thermal budget of 950°C, 30s could serve as a proper choice for gate dopants activation. © Physica Scripta 2004.

Author

Mikael Johansson

Chalmers

M. Y. A. Yousif

Chalmers, Microtechnology and Nanoscience (MC2), Solid State Electronics

Per Lundgren

Chalmers, Microtechnology and Nanoscience (MC2)

Stefan Bengtsson

Chalmers, Microtechnology and Nanoscience (MC2)

Physica scripta. Topical Issues

0281-1847 (ISSN)

Vol. T114 97-99

Subject Categories

Materials Engineering

Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1088/0031-8949/2004/T114/024

More information

Latest update

9/10/2018