Design trade-offs in energy efficient NoC architectures
Paper in proceeding, 2015

This paper studies design trade-offs in energy efficient Networks-on-Chip by evaluating every network architecture that derives when we apply all possible variations of design-configuration parameters on a baseline 2D mesh. Network separation (P), concentration (C), express channels (X), flit widths (W), and virtual channels (V). Our comperative analysis selects the network architecture configuration that gives the best energy delay product (EDP) while allowing a maximum area margin of 15% over the most energy efficient configuration of the baseline.


A. Psathakis

Foundation for Research and Technology Hellas (FORTH)

Vasileios Papaefstathiou

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

M. Katevenis

Foundation for Research and Technology Hellas (FORTH)

University of Crete

Dionisios N. Pnevmatikatos

Technical University of Crete

Foundation for Research and Technology Hellas (FORTH)

8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014; Ferrara; Italy; 17 September 2014 through 19 September 2014


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Computer Engineering



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