High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding
Paper in proceedings, 2013

Binary Signed-Digit Residue Number System (BSD-RNS) has been proposed in the literatures as an appropriate number system to perform the arithmetic operations in parallel. BSD-RNS addition is the basic operation and improving its performance results in efficient VLSI arithmetic circuits. Here, we present a new architecture for carry-free BSD-RNS addition utilizing a recently proposed posibit and negabit BSD representation. Compared to 2's complement BSD-RNS adder, the proposed architecture has 21% less delay. Besides, for a same delay (0.6ns), we obtain 48% less area and 28% less power than the most efficient existing BSD-RNS adder.

Carry-Free Addition

Binary Signed Digit

Residue Number System

Author

S. Timarchi

Shahid Beheshti University

M. Saremi

Shahid Beheshti University

M. Fazlali

Shahid Beheshti University

Georgi Gaydadjiev

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013; Istanbul; Turkey; 7 October 2013 through 9 October 2013

2324-8440 (eISSN)

58-59

Subject Categories

Computational Mathematics

DOI

10.1109/VLSI-SoC.2013.6673248

ISBN

978-147990524-9

More information

Created

10/7/2017