FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration
Journal article, 2015

The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) EU FP7 project, aims to ease the design and implementation of dynamically changing hardware systems. Our motivation stems from the promise reconfigurable systems hold for achieving high performance and extending product functionality and lifetime via the addition of new features that operate at hardware speed. However, designing a changing hardware system is both challenging and time-consuming. FASTER facilitates the use of reconfigurable technology by providing a complete methodology enabling designers to easily specify, analyze, implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology. Our tool-chain supports both coarse- and fine-grain FPGA reconfiguration, while during execution a flexible run-time system manages the reconfigurable resources. We target three applications from different domains. We explore the way each application benefits from reconfiguration, and then we asses them and the FASTER tools, in terms of performance, area consumption and accuracy of analysis.

Dynamic reconfiguration

Partial reconfiguration

Micro-reconfiguration

Verification

Runtime system

Reconfigurable computing

Author

Dionisios N. Pnevmatikatos

Foundation for Research and Technology Hellas (FORTH)

Kyprianos D. Papadimitriou

Foundation for Research and Technology Hellas (FORTH)

T. Becker

Imperial College London

P. Bohm

Imperial College London

A. Brokalakis

Synelixis Solutions

K. Bruneel

Ghent university

Catalin Ciobanu

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

T. Davidson

Ghent university

Georgi Gaydadjiev

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)

K. Heyse

Ghent university

W. Luk

Imperial College London

X. Niu

Imperial College London

Ioannis Papaefstathiou

Synelixis Solutions

D. Pau

STMicroelectronics, Geneva

O. Pell

Maxeler Technologies

Christian Pilato

Polytechnic University of Milan

M. D. Santambrogio

Polytechnic University of Milan

Donatella Sciuto

Polytechnic University of Milan

D. Stroobandt

Ghent university

T. Todman

Imperial College London

E. Vansteenkiste

Ghent university

Microprocessors and Microsystems

0141-9331 (ISSN)

Vol. 39 4-5 321-338

Facilitating Analysis and Synthesis Technologies\nfor Effective Reconfiguration (FASTER)

European Commission (FP7), 2011-09-01 -- 2014-11-30.

Subject Categories

Computer Science

DOI

10.1016/j.micpro.2014.09.006

More information

Latest update

9/6/2018 2