GaAs Flip Chip Evaluation in the 3 to 110 GHz Range

Other conference contribution, 2004

In the European MEDEA+ packaging project HIMICRO (Novel Packaging Technologies for Highly Integrated MICRO modules for Next Generation Telecom and Automotive Products), we address the problem to flip chip mount unbumped chips for prototyping and low volume production as a step on the way towards higher volumes. Two different flip chip (FC) interconnect technologies have been evaluated by measurements of the scattering parameters after initial electromagnetic (EM) simulation of the general structure: 1. Thermo compression (TC) flip chip bonding of the MMICs to gold ball bumps bonded on the substrate 2. TC flip chip bonding of the MMICs to electrolytically plated gold pillars on the substrate Also, the possible occurrence of parasitic parallel plate (PPL) modes in flip chip assemblies with microstrip (MS), coplanar waveguide (CPW) and backside plated coplanar waveguide (BPCPW) MMICs (Microwave Monolithic Integrated Circuits) is investigated and compared. In addition, the effect of adding a resistive layer on the thin film substrate is evaluated.