Studies of hysteresis in capacitance and current characteristics of flexible graphene field-effect transistors

Paper in proceeding, 2017

Owing to the unique combination of mechanical and electrical properties of graphene, e.i., flexibility and high carrier velocity, it is a promising material for emerging applications in flexible high frequency electronics. One of the challenges in the development of reliable high performance devices is associated with impurities, which are normally present at the graphene/dielectric interfaces. Impurities reduce the carrier mobility via scattering (Ref. 1) and introduce interface states. Interface states can trap and detrap charge carriers which typically leads to hysteresis. Fig.1 and Fig.2 show hysteresis in the gate capacitance and drain current versus gate voltage dependences measured in this work in the graphene field-effect transistors (GFETs) on flexible PET substrates. It is important to clarify the nature and the distribution of traps to be able to improve the GFET design, materials and fabrication process in the development of hysteresis-free flexible GFETs. In this work, we continue developing the model (Ref. 2), which describes the influence of interface states on gate capacitance-voltage and drain resistancevoltage characteristics and allows for reasonable good fitting of the forward sweep (Fig.1 and Fig.2, solid lines). Here, we include also the backward sweep, which, as it can be seen, requires more advanced modelling, taking into account trapping/ de-trapping dynamics and the analysis of interface state distribution. This work helps to clarify the origin of hysteresis in greater depth and allows for combination with other models, e.g., include hysteresis effects in the model of the responsivity of flexible GFET THz power detectors [3].