LLC-guided data migration in hybrid memory systems
Paper in proceedings, 2019

Although 3D-stacked DRAM offers substantially higher bandwidth than commodity DDR DIMMs, it cannot yet provide the necessary capacity to replace the bulk of the memory. A promising alternative is to use flat address space, hybrid memory systems of two or more levels, each exhibiting different performance characteristics. One such existing approach employs a near, high bandwidth 3D-stacked memory, placed on top of the processor die, combined with a far, commodity DDR memory, placed off-chip. Migrating data from the far to the near memory has significant performance potential, but also entails overheads, which may diminish migration benefits or even lead to performance degradation. This paper describes a new data migration scheme for hybrid memory systems that takes into account the above overheads and improves migration efficiency and effectiveness. It is based on the observation that migrating memory segments, which are (partly) present in the Last-Level Cache (LLC) introduces lower migration traffic. Our approach relies on the state of the LLC cachelines to predict future reuse and select memory segments for migration. Thereby, the segments are migrated when present (at least partly) in the LLC incurring lower cost. Our experiments confirm that our approach outperforms current state-of-the art migration designs improving system performance by 12.1% and reducing memory system dynamic energy by 13.2%.

Author

Evangelos Vasilakis

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Computer Systems

Vasileios Papaefstathiou

Foundation for Research and Technology Hellas (FORTH)

Pedro Petersen Moura Trancoso

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Computer Systems

Ioannis Sourdis

Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers), Computer Systems

Proceedings - 2019 IEEE 33rd International Parallel and Distributed Processing Symposium, IPDPS 2019

932-942 8820989

33rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2019
Rio de Janeiro, Brazil,

Energy-efficient Heterogeneous COmputing at exaSCALE (ECOSCALE)

European Commission (Horizon 2020), 2015-10-01 -- 2018-12-31.

Subject Categories

Computer Engineering

Communication Systems

Computer Systems

DOI

10.1109/IPDPS.2019.00101

More information

Latest update

11/6/2019