An 11 GS/s 2×10 b 20–26 GHz Modulator using Segmented Non-Linear RF-DACs and Non-Overlapping LO signals
Paper in proceeding, 2022

We present a Cartesian I/Q modulator based on dual 10-bit RF-DACs. Non-overlapping LO signals and a segmented RF-DAC architecture with scaled bit currents contribute to good linearity and allow low-complexity DPD. Unit-cell flip-flops with a balanced clock distribution enable a high sample rate. Drive slope control for data switches reduce out-of-band emissions. Implemented in 22nm FDSOI CMOS, the modulator operates up to 26GHz with a maximum sample rate of 11 GS/s. The modulator is used to demonstrate transmission of a 64QAM signal at 13.2 Gb/s, a 256QAM signal at 7.33 Gb/s, and an OFDM signal comprising four aggregated 400-MHz 64QAM channels at an EVM of 6.43 %. The results demonstrate the potential of the proposed modulator architecture for realization of ultra wideband transmitters for high performance mm-wave systems.

RF-DAC

CMOS

IQ modulator

Author

Victor Åberg

Embedded Electronics Systems and Computer Graphics

Christian Fager

Chalmers, Microtechnology and Nanoscience (MC2), Microwave Electronics

Rui Hou

Ericsson

Lars Svensson

Embedded Electronics Systems and Computer Graphics

Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium

15292517 (ISSN)

Vol. 2022-June 143-146
9781665496117 (ISBN)

2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)
Denver, USA,

Areas of Advance

Information and Communication Technology

Infrastructure

Kollberg Laboratory

Subject Categories

Telecommunications

Signal Processing

Other Electrical Engineering, Electronic Engineering, Information Engineering

DOI

10.1109/RFIC54546.2022.9863143

More information

Latest update

7/17/2024