Development of the high performance DSP architecture for the RSFQ interference canceller
Paper in proceedings, 2004

A new architecture and a new design method have been developed for the implementation of an RSFQ Successive Interference Canceller. The architecture is based on the complete pipe-lining of the operations with dynamic on-chip memory and bit-parallel processing. The design method is based on the fixed RSFQ schematic library having such an important features like arbitrary connectivity within a library and stable timing parameters. The hardware complexity is evaluated for the case of the 48 simultaneously operated channels in fading multipath environment transmitting at rate 300 Kb/s.


Anna Kidiyarova-Shevchenko

Chalmers, Microtechnology and Nanoscience (MC2)

Konstantin Platov

Chalmers, Microtechnology and Nanoscience (MC2), Quantum Device Physics

Hongxia Zhao

Chalmers, Signals and Systems, Communication and Antenna Systems, Communication Systems

Elena Tolkacheva

Chalmers, Microtechnology and Nanoscience (MC2), Quantum Device Physics

Irina Kataeva

Chalmers, Microtechnology and Nanoscience (MC2)

Institute of Physics Conference Series

0951-3248 (ISSN)

Vol. 181 187-194

Subject Categories

Electrical Engineering, Electronic Engineering, Information Engineering

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