Feasibility Study of FPGA-Based Equalizer for 112-Gbit/s Optical Fiber Receivers
Paper in proceeding, 2012
With ever increasing demands on spectral efficiency, complex
modulation schemes are being introduced in fiber communication. However, these schemes are challenging to implement as they drastically increase the computational burden at the fiber receiver’s end. We perform a feasibility study of implementing a 16-QAM 112-Gbit/s decision directed equalizer on a state-of-the-art FPGA platform. An FPGA offers the reconfigurability needed to allow for modulation scheme updates, however, its clock rate is limited. For this purpose, we introduce a new phase correction technique to significantly relax the delay requirement on the critical phase-recovery feedback loop.
Feed-back loop
Modulation schemes
Complex modulation
Feasibility studies
Decision-directed
In-fiber
Phase corrections
Clock rate
Computational burden
Spectral efficiencies
Reconfigurability
Author
Fredrik Toft
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Niclas Rousk
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
Jonas Mårtensson
RISE Research Institutes of Sweden
Marco Forzati
RISE Research Institutes of Sweden
Bengt-Erik Olsson
Ericsson
Per Larsson-Edefors
Chalmers, Computer Science and Engineering (Chalmers), Computer Engineering (Chalmers)
ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems
3234-3237 6272013
978-1-4673-0218-0 (ISBN)
Areas of Advance
Information and Communication Technology
Energy
Driving Forces
Sustainable development
Innovation and entrepreneurship
Subject Categories
Other Electrical Engineering, Electronic Engineering, Information Engineering
DOI
10.1109/ISCAS.2012.6272013
ISBN
978-1-4673-0218-0