RSFQ Parallel Multiplier
Konferensbidrag (offentliggjort, men ej förlagsutgivet), 2003

This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems. We have designed the parallel multiplier which consists of N M-bits serial adders based on the T1 cells for M ×N sign multiplication. This multiplier consumes 74×M×N Josephson junctions. The 2-bit and 4-bit parallel multipliers have been designed for TRW’s 8 kA/cm2 process. The maximum VHDL simulated clock speed and one bit effective area are 39 GHz and 300 × 300 μm2 correspondingly.

Multiplier

RSFQ

Parallel

Författare

Irina Kataeva

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Henrik Engseth

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Elena Tolkacheva

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Anna Kidiyarova-Shevchenko

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

Applied Superconductivity 2003, EUCAS sorrento Italy, conference series number 181

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Övrig annan teknik

Annan elektroteknik och elektronik