Experimental Verification of Superconductor Digital Circuits
Licentiatavhandling, 2005

Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) offers more than 50 times advantages in speed and $100$ times less power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP) for multi-user detection in a 3G wireless systems being developed at Chalmers University. The being developed DSP is targeting record performance of 30 giga operation per second. It consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and external semiconductor memory. Such an architecture allows to implement memory fetch at 30 GHz speed. The development of the complex high speed cryogenic digital system requires solution of the several interface, packaging and testing problems: cooling down to $4$ K operational temperature, magnetic shielding, multi channel high bandwidth interfacing of low voltage signals in a hybrid RSFQ-CMOS memory, and implementation of the high speed test setups. The key steps towards the solution of these problems is the subject of this thesis. The main emphasis of the work is on the development of room temperature interfacing equipment for digital superconductor electronics and experimental testing of RSFQ DSP components. The work has involved the following parts: development of the low frequency cryoprobe, design of the full system MCM cryoprobe, low frequency testing of RSFQ components and development of a high speed testbench. A large part of the work is connected to the experimental verification of DSP components and their gradual improvement against functionality. The RSFQ circuits tested were fabricated at advanced multilayered processes available from NGST 8 kA/cm^2, HYPRES 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. A number of different designs where experimentally measured at low speed using the data acquisition system Octopux. In order to investigate the influence of bias-supply lines on RSFQ circuit operation, measurements were performed to characterize the mutual inductance between different layers. For verification of high bandwidth interconnects, passive micro-strip lines with drivers and receivers where tested. From the being developed RSFQ DSP several of the key logic blocks have been experimentally tested at low speed: 4*4, 5*5, a new 4*4 parallel multiplier, 20*5 and 4*15 shift registers memories. For high speed testing a testbench employing RSFQ shift registers for clock injection/capture was successfully implemented and verified up to 33.5 GHz.

heatload

MCM

high frequency test

RSFQ

Superconductivity

Chalmers main library
Opponent: Dag Winkler

Författare

Henrik Engseth

Chalmers, Mikroteknologi och nanovetenskap (MC2), Fasta tillståndets elektronik

1652-0769 (ISSN)

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Artikel i vetenskaplig tidskrift

Time-Delay Optimization of RSFQ Cells

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Artikel i vetenskaplig tidskrift

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Paper i proceeding

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Superconducting Science and technology,; Vol. 19(2006)p. S376-S380

Artikel i vetenskaplig tidskrift

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Konferensbidrag (offentliggjort, men ej förlagsutgivet)

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Superconducting Science and technology,; Vol. 19(2006)p. S381-S386

Artikel i vetenskaplig tidskrift

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Applied superconductivity 2003, EUCAS Sorrento, Italy.,; (2003)

Artikel i vetenskaplig tidskrift

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Superconductor Science and Technology,; Vol. 18(2005)p. 1065-1072

Artikel i vetenskaplig tidskrift

Ämneskategorier

Övrig annan teknik

Reglerteknik

Technical report MC2 - Department of Microtechnology and Nanoscience, Chalmers University of Technology: MC2-49

Chalmers main library

Opponent: Dag Winkler

Mer information

Skapat

2017-10-06