Test bed for verification of RSFQ DSP
Poster (konferens), 2005
In this work we are going to present a design of a test bed for a superconducting high speed Digital Signal Processor (DSP), designed to run basic matrix-matrix multiplications at a speed of 30 Gops. Main application of the being developed DSP is multi-user detection in a 3G wireless system. The DSP consist of a digital core, RSFQ Multiply Accumulate unit (MAC) and a memory. The memory is divided into two parts: room temperature memory for matrix storing and the fast RSFQ shift register based memory for storing vectors. An RSFQ fast shift-register-memory is located on a Multi Chip Module (MCM) board together with the digital core. Communication between room temperature memory and the cryogenic MCM is performed with an asynchronous protocol at 500 MHz speed for a single channel. To verify the DSP operation a room temperature acquisition system receives output data from the DSP at 7M bit/s. The overall structure of the test bed comprises two room temperature blocks for matrix storing and data acquisition controlled by external data source and interface circuitry between semiconductor and superconductor parts. We are going to present results of the heat load calculations, design and specifications of the high speed communication channels, design of the biasing network and of the MCM board.
Succesive Interference Canceller