Electrical Characterization of Metal-Oxide-Silicon Structures with Ultra Thin Oxide Layers
Metal-oxide-semiconductor (MOS) structures with very thin (2 - 4 nm) oxide layers thermally grown on silicon have been electrically characterized regarding oxide and interface defects and concerning the direct tunnel current through the oxide. This thesis comprises eight papers which deal with
the appearance of oxide charge during electrical stress (papers A, D, E),
the beneficial effect on the defect density of low-temperature (up to 350 °C) post-metallization annealing (PMA) (paper A, B, C, G), and
the effect of temperature and choice of metal for the tunnel current (paper F, H).
An introductory overview of the relevant field of research is also given.
It is found that PMA of metal-tunnel oxide-silicon (MTOS) devices at 350 °C for fifteen minutes reduces the tunnel current and the densities of silicon-oxide interface defects by at least an order of magnitude. Evidence for a dependence of the passivation reaction on the charge state of the interface defects is presented.
Electrical stress of annealed devices leads to the appearance of positive charge in the oxide. This charge can be monitored either by the induced tunnel current increase or by the accompanying change of capacitance for the device. The positive charge is found to be neutralized in a slow process, which is dependent on the temperature and the average oxide electric field.
The effect of temperature and choice of metal on the direct tunnel current through the oxide can be described by the commonly used model relying on an effective mass description of the system and the WKB approximation.
In view of the persistent trend of scaling down silicon-based integrated circuit designs, studies of very thin oxide layers on silicon are of increasing relevance; not only to inventive designers of esoteric electronic devices, but to anyone relying on the safe operation of electronic office or household appliances in the Information Age of tomorrow.