Towards a Power and Performance Simulation Framework for Parallel DSP Architecture
High performance, low power and low cost will continue to be driving factors for digital signal processor (DSP) and embedded computer systems of the future. Recent improvements of semiconductor technology have led to faster circuits, higher density, and smaller dimensions. However, along with technology scaling there are still many difficult challenges for future electronic and computer system design, one of them is power consumption. There is a lot of research efforts dedicated for reducing both dynamic and static power consumption in all the design
levels ranging from the circuit-level to the architecture-level and the algorithm-level. In all these levels performance-power simulation/estimation tools play a very important, even decisive role.
This thesis describes in detail our ongoing research work on designing and im-plementing an architecture-level cycle-accurate power-performance simulator for parallel DSP architectures (DSP-PP). The DSP-PP uses the suggested White-box Table-based Total Power Consumption (WTTPC) estimation approach offering both rapid and accurate architectural level power estimation models for proces-sor
components with regular structures (such as SRAM arrays) based on tables of power values. This approach offers relatively simple high-accuracy architecture-level
power estimation models accounting for both dynamic and static power consumption.
The DSP-PP simulator, implemented using C++ and SystemC libraries, simulates
an extended version of the ManArray parallel DSP architecture. DSP-PP produces performance data (i.e. number of clock cycles) and power estimates
while running executable programs. By varying the configuration of the architecture, the user can rapidly explore the power and performance design space.
Power estimation models
Power estimation simulation