Compiler-Based Approaches to Reduce Memory. Access Penalties in Cache Coherent Multiprocessors
Doktorsavhandling, 1997

To reduce the average time needed to perform a read or a write access in a multiprocessor, a cache is associated with each processor. A hardware mechanism is used to ensure that the replicated cache copies are consistent. This mechanism employs a protocol which controls when a node may read and/or write a shared data item. The time a processor is waiting for actions of the protocol to be performed, called the memory access penalty, limits the performance that can be achieved.

compiler analysis

hardware support

performance evaluation

memory access penalty

cache coherent multiprocessors

Författare

Jonas Skeppstedt

Institutionen för datorteknik

Ämneskategorier

Data- och informationsvetenskap

ISBN

91-7197-452-0

Technical report - School of Electrical and Computer Engineering, Chalmers University of Technology, Göteborg, Sweden: 305

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 1280