Tuning software phase-locked loop for series-connected converters
Artikel i vetenskaplig tidskrift, 2005
Accurate phase information is crucial for most of the modern power-electronics apparatus such as the static sedes compensator (SSC). A software phase-locked loop (SPLL) has been proposed in literature to obtain phase and frequency information of the grid voltage. Either a lead/lag filter or a proportional-plus-integral (PI) controller is employed to control the performance of the SPLL. In this paper, a criterion to tune the SPLL is discussed and the gains of the PI-controller are determined to obtain the desired performance. The proposed criterion is based on the fact that a phase shift of the grid voltage is sensed as a frequency deviation by the load. If the deviation of the grid frequency is kept within the range ±1 Hz, most of the loads function properly. Hence and by the SSC. the response of the phase angle of the load voltage is designed to follow the grid voltage angle while satisfying the frequency range at all times. Consequently, the gains of the PI-regulator of the SPLL are dependent on the maximum phase shift of the grid voltage. Unbalanced grid voltages are separated into positive-and negative-sequence components and the SPLL is locked to the positive sequence. The response of the SPLL has been evaluated by using PSCAD/EMTDC simulation package.