Switch-Level Fault Simulation Based on Local Algorithms
Doktorsavhandling, 1995

The presence of realistic faults in CMOS networks, such as shorts and opens, frequently gives rise to intermediate voltage values. At the switch level, these values result in undetermined logic states (X) which are likely to propagate to the outputs, causing uncertainty in the estimation of test set efficiency. The first part of this thesis presents event-driven switch-level algorithms for handling abnormal situations occurring in networks in the presence of faults. A proposal is made for an extension to the traditional single-dominance node model which efficiently solves conflicts that may occur between adjacent nodes assigned the X state and thereby significantly reduces the spread of X values as compared with traditional methods. The degradation of confidence in fault detection measures owing to undetermined output values is discussed. A new switch-level model is presented which allows an arbitrary number of dominant signals associated with the state of a node. The strength of several signal contributions can thereby be taken into account when the logic state is computed. It is shown that the error bounds in the voltage prediction, in many cases, are significantly reduced in comparison with traditional models. An efficient two-pass fault simulation algorithm is presented which, during the first pass, simulates the entire network with a less sophisticated node model and detects any faulty situations in a subnetwork. Second, this subnetwork is evaluated under the proposed multiple-dominance node model. The second part of this thesis deals with the modeling of particle-induced transients in combinational networks and includes results from physical fault injection experiments. A novel technique is presented for determining the relative frequency of Single Event Upsets (SEUs) originating from combinational logic and direct hits in latches. A new switch-level algorithm is proposed for the simulation of transients in combinational networks in which a first-order RC model is applied to the fault injection node for predicting the width of a voltage pulse. The fact that transients may fade out during propagation is efficiently modeled by taking into account the pulse width and the topology of subsequent transistor stages.

switch level

fault propagation

fault simulation

physical fault injection

short faults

stuck-at faults

fault modeling


self-checking circuits

multiple dominance


Peter Dahlgren

Institutionen för datorteknik


Data- och informationsvetenskap



Technical report - School of Electrical and Computer Engineering, Chalmers University of Technology, Göteborg, Sweden: 270

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 1098

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