Techniques to Reduce Inefficiencies in Hardware Transactional Memory Systems
Doktorsavhandling, 2011
intermediate checkpoint
conflicting address prediction
Bloom filter
conflict resolution
multiprocessor
speculative buffer overflow
parallel programming
5C model for cache-misses
transactional memory
conflict classification
starvation
Författare
Mridha Mohammad Waliullah
Chalmers, Data- och informationsteknik, Datorteknik
Efficient Partial Roll-backing Mechanism for Transactional Memory Systems
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics),;Vol. 6590(2008)p. 256-274
Artikel i vetenskaplig tidskrift
Efficient Management of Speculative Data in Hardware Transactional Memory Systems
2008 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2008; Samos; Greece; 21 July 2008 through 24 July 2008,;(2008)p. 158-164
Paper i proceeding
Simple Performance Optimization Techniques for Hardware Transactional Memory Systems
Proceedings of the Third Swedish Workshop on Multicore Computing,;(2010)
Övrigt konferensbidrag
Schemes for avoiding starvation in transactional memory systems
Concurrency Computation Practice and Experience,;Vol. 21(2009)p. 859-873
Artikel i vetenskaplig tidskrift
LV*: A Low Complexity Lazy Versioning HTM Infrastructure
Proceedings - 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, IC-SAMOS 2010,;(2010)p. 231-240
Paper i proceeding
Ämneskategorier
Datorteknik
Styrkeområden
Informations- och kommunikationsteknik
ISBN
978-91-7385-486-3
Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie: 3167
Technical report D - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University: 75
Sal EE
Opponent: Professor Ian Watson