A Novel Approach to High Level Switching Activity Modeling with Applications to Low Power DSP System Synthesis
Artikel i vetenskaplig tidskrift, 2001

We address high-level synthesis of low-power digital signal processing (DSP) systems by using efficient switching activity models. We present a technology-independent hierarchical scheme that can be easily integrated into current communications/DSP CAD tools for comparing the relative power/performance of two competing DSP designs without specific knowledge of transistor-level details. The basic building blocks considered for such systems are a full adder, a half adder, and a one-bit delay. Estimates of the switching activity at the output of these primitives are used to model the activity in more complex building blocks of DSP systems. The presented hierarchical method is very fast and simple. The accuracy of estimates obtained using the proposed approach is shown to be within 4% of the results obtained using extensive bit-level simulations. Our approach shows that the choice of multiplier/multiplicand is important when using array multipliers in a datapath. If the input signal with smaller mean square value is chosen as the multiplicand, almost 20% savings in switching activity can be achieved. This observation is verified by an analog simulation using a 16 x 16 bit array multiplier implemented in a 0.6-mu process with 3.3 V supply voltage.

low power synthesis

input reordering

power estimation

switching activity

high-level modeling


Magnus Lundberg

Chalmers, Signaler och system, Signalbehandling och medicinsk teknik, Signalbehandling

Khurram Muhammad

Kaushik Roy

Sarah Kate Wilson

IEEE Transactions on Signal Processing

1053-587X (ISSN)

Vol. 49 12 3157-3167


Data- och informationsvetenskap



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