Comparing scalability prediction strategies on an SMP of CMPs
Paper i proceeding, 2010

Diminishing performance returns and increasing power consumption of single-threaded processors have made chip multiprocessors (CMPs) an industry imperative. Unfortunately, poor software/hardware interaction and bottlenecks in shared hardware structures can prevent scaling to many cores. In fact, adding a core may harm performance and increase power consumption. Given these observations, we compare two approaches to predicting parallel application scalability: multiple linear regression and artificial neural networks (ANNs). We throttle concurrency to levels with higher predicted power/performance efficiency. We perform experiments on a state-of-the-art, dual-processor, quad-core platform, showing that both methodologies achieve high accuracy and identify energy-efficient concurrency levels in multithreaded scientific applications. The ANN approach has advantages, but the simpler regression-based model achieves slightly higher accuracy and performance. The approaches exhibit median error of 7.5% and 5.6%, and improve performance by an average of 7.4% and 9.5%, respectively.


Karan Singh

Cornell University

M. Curtis-Maury

Network Appliance, Inc.

Sally A McKee

Chalmers, Data- och informationsteknik, Datorteknik

F. Blagojevic

Lawrence Berkeley National Laboratory

Dimitrios S. Nikolopoulos

Foundation for Research and Technology Hellas (FORTH)

B. R. De Supinski

Lawrence Livermore National Laboratory

M. Schulz

Lawrence Livermore National Laboratory

Lecture Notes in Computer Science

0302-9743 (ISSN)

Vol. 6271 143-155


Data- och informationsvetenskap