Feasibility Study of FPGA-Based Equalizer for 112-Gbit/s Optical Fiber Receivers
Paper i proceeding, 2012

With ever increasing demands on spectral efficiency, complex modulation schemes are being introduced in fiber communication. However, these schemes are challenging to implement as they drastically increase the computational burden at the fiber receiver’s end. We perform a feasibility study of implementing a 16-QAM 112-Gbit/s decision directed equalizer on a state-of-the-art FPGA platform. An FPGA offers the reconfigurability needed to allow for modulation scheme updates, however, its clock rate is limited. For this purpose, we introduce a new phase correction technique to significantly relax the delay requirement on the critical phase-recovery feedback loop.

Complex modulation

Decision-directed

Computational burden

Feed-back loop

Reconfigurability

Phase corrections

Feasibility studies

Modulation schemes

In-fiber

Spectral efficiencies

Clock rate

Författare

Fredrik Toft

Chalmers, Data- och informationsteknik, Datorteknik

Niclas Rousk

Chalmers, Data- och informationsteknik, Datorteknik

Jonas Mårtensson

Acreo AB

Marco Forzati

Acreo AB

Bengt-Erik Olsson

Ericsson Microwave Systems AB

Per Larsson-Edefors

Chalmers, Data- och informationsteknik, Datorteknik

ISCAS 2012 - 2012 IEEE International Symposium on Circuits and Systems

3234-3237 6272013

Styrkeområden

Informations- och kommunikationsteknik

Energi

Drivkrafter

Hållbar utveckling

Innovation och entreprenörskap

Ämneskategorier

Annan elektroteknik och elektronik

DOI

10.1109/ISCAS.2012.6272013

ISBN

978-1-4673-0218-0