Manufacturability in the Nanometer Era: Regularity considerations in VLSI Circuits
Licentiatavhandling, 2012

Each reduction of the technology node has, along with improvements in IC fabrication technology, been the main driver in delivering the demand for function rich, integrated mobile electronics that are so prevalent. As devices keep growing smaller and geometries approach the order of a few atomic layers, it is increasingly difficult to achieve cost-effective mass production for reasons related to performance and fabrication capability. The small geometries have made visible quantum-mechanical effects that are not seen in micron scale geometries. These effects result in parametric variations and additionally, limitations in the lithographic capability means that cost effective fabrication is possible only at considerable investment. Adopting regularity in layout has been prescribed as a means to mitigate variability in small geometries. This measure however, is not widely adopted due to the lack of a structured methodology in implementing such layouts. This thesis aims to study the hurdles existing in implementing such a methodology, at different levels of abstraction. Increasing design complexity has led to the widespread use of standard cell methodology to enable shorter design cycles. Typically, the place and route tools rely on heuristic algorithms that tradeoff run time against performance constraints. The first part of this thesis presents a novel methodology for regular layout of standard cells in a layout exploration scenario. The design flow is applied to arithmetic circuits like log-depth multipliers and shifters in order to assess various tradeoffs. The second part of this thesis discusses regularity from a circuits perspective rather than a design perspective. The different factors affecting the implementation of a regular layout are discussed. In the latter half we discuss aspects of manufacturing, the sources of variability, assessment techniques and the impact of regularity on mitigating the negative aspects of technology scaling in the face of engineering limitations. Finally, the studies will be summarized and the scope of future work will be presented.

Regular Fabrics

Shifters

Barrel Shifter

ASIC

TDM

Bricks

Wired

Transistor

VLSI.

Multipliers

CMOS

HPM

Regularity

SoC

Arithmetic

Circuits

Room EE, EDIT Building, Chalmers tekniska högskola, Campus Johanneberg
Opponent: Asst. Prof. Joachim Rodrigues, Lund University

Författare

Kasyab Parmesh Subramaniyan

Chalmers, Data- och informationsteknik, Datorteknik

Styrkeområden

Informations- och kommunikationsteknik

Ämneskategorier

Annan elektroteknik och elektronik

Room EE, EDIT Building, Chalmers tekniska högskola, Campus Johanneberg

Opponent: Asst. Prof. Joachim Rodrigues, Lund University