Multi-Mode Datapath Circuits for Flexible and Energy-Efficient Computing
Doktorsavhandling, 2013

Tailored to run domain-specific applications under very strict constraints on, for example, real-time performance and power dissipation, embedded systems rarely can be implemented on general-purpose computing platforms. Rather, the embedded processor's architecture and implementation technology should be fine tuned to the needs of the particular embedded system. However, this is not possible since system complexities are booming, while system implementation resources are limited. Thus, the design of an embedded system is bound to result in tradeoffs between several conflicting requirements. As we will show, to some extent, multi-mode circuits can facilitate these tradeoffs and offer new embedded processor configurations. In this thesis, several approaches to designing energy-efficient embedded processor datapaths are proposed. The overall thesis theme is multi-mode datapath circuits, which are circuits that can operate in different modes, allowing for configuration and adaptation to the applications currently running on the processor. While the main contributions of this thesis are on architecture and circuitry of multi-mode datapath circuits, the thesis also considers processor integration and energy-aware design exploration. The first part of the thesis presents the existing FlexCore processor design environment, which enables holistic processor system evaluations of, for example, multi-mode circuits. Beside a design exploration methodology that allows for application customization, we demonstrate processor integration of a multi-mode cyclic-redundancy-checking (CRC) accelerator. The second part of the thesis concentrates on high-speed and energy-efficient multiply-accumulate (MAC) architectures, which can accelerate signal processing applications of embedded processors, leading to significant energy savings at the application level. In the third and last part, the technique of power gating is applied to exploit computing idle times and unused hardware in narrow-width computation of datapath circuits for leakage energy reductions.


power gating



energy efficiency

EA, EDIT-building, Rännvägen 6, Chalmers University of Technology, Göteborg, Sweden
Opponent: Associate Professor Youngsoo Shin, Korea Advanced Institute of Science and Technology, Korea


Tung Hoang

Chalmers, Data- och informationsteknik, Datorteknik

Power Gating Multiplier of Embedded Processor Datapath

Proceedings of 7th Conference on Ph.D Research in Microelectronics and Electronics (PRIME) Madonna di Campiglio, Trento; 3 July 2011 through 7 July 2011,; (2011)p. 41-44

Paper i proceeding

Design Space Exploration for an Embedded Processor with Flexible Datapath Interconnect

Proceedings of IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP),; (2010)p. 55-62

Paper i proceeding

Data-Width-Driven Power Gating of Integer Arithmetic Circuits

Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Amherst, 19-21 August 2012,; (2012)p. 237-242

Paper i proceeding

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit

IEEE Transactions on Circuits and Systems I: Regular Papers,; Vol. 57(2010)p. 3073-3081

Artikel i vetenskaplig tidskrift

Double Throughput Multiply-Accumulate Unit for FlexCore Processor Enhancements

23rd IEEE International Parallel and Distributed Processing Symposium, IPDPS 2009; Rome; Italy; 23 May 2009 through 29 May 2009,; (2009)

Paper i proceeding

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor

Proceedings of Euromicro Conference on Digital System Design (DSD),; (2010)p. 675-680

Paper i proceeding


Informations- och kommunikationsteknik


Inbäddad systemteknik


Annan elektroteknik och elektronik

Technical report D - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie

EA, EDIT-building, Rännvägen 6, Chalmers University of Technology, Göteborg, Sweden

Opponent: Associate Professor Youngsoo Shin, Korea Advanced Institute of Science and Technology, Korea

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