Design of superconductor digital circuits for a 30 GHz DSP and for interface to qubits
Superconducting digital technology based on Rapid Single Flux Quantum logic (RSFQ) is a digital technology characterized by high speed, low power consumption and low operational temperatures. RSFQ is attractive for many applications and in particular for high frequency Digital Signal Processing (DSP) and for digital control of mK devices like superconducting qubits. Due to the 30 GHz clock speed, RSFQ DSP could be used to implement a Successive Interference Canceller for multi-user detection in a 3G wireless systems. The being developed DSP consists of a digital core, an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory and external semiconductor memory.
The first part of this thesis is focusing on architecture and implementation of the hierarchical CMOS-RSFQ hybrid memory for the RSFQ DSP. The architecture of
the RSFQ cache is optimized in order to reach the highest speed and reliable data communication with CMOS memory. Aspects of block synchronization between
the RSFQ cache and the RSFQ digital core are discussed and solved using a new developed RSFQ gate, C3. For design of different components of the DSP, a design
approach based on validated VHDL models is proposed and experimentally verified.
The second part of this thesis is focusing on the design of
low-dissipative RSFQ circuits for interface to the superconducting qubits. Power dissipation of
RSFQ circuits is minimized. A low-temperature thermal model of resistively shunted Josephson
junctions is developed and applied to optimize the shape of the shunt resistors in order to reduce their electron temperature. Depending on the available fabrication
process the lowest noise temperature of RSFQ circuit can be in the range from 90 mK to 180 mK.