A 3.5GHz 32mW 150nm Multiphase Clock Generator for High-Performance Microprocessors
Paper i proceeding, 2003

A 3.5GHz 8-phase all-digital clock generator is fabricated in 150nm CMOS to achieve scalable 1.7x frequency-range and 9ps end-to-end time resolution measured at 1.6V and 110°C. A closed-to-open loop control scheme enables 32mW open-loop power consumption, 300μW at clock gate-off, zero-cycle response during clock re-enable, and <4% static phase error.

Författare

A. Alvandpour

R.K. Krishnamurthy

Daniel Eckerbert

Chalmers, Institutionen för datorteknik

S. Apperson

B. Bloechel

S. Borkar

Digest of Technical Papers. IEEE International Solid-State Circuits Conference, 9-13 February 2003

0193-6530 (ISSN)

Ämneskategorier

Datorteknik

DOI

10.1109/ISSCC.2003.1234230

ISBN

0-7803-7707-9

Mer information

Skapat

2017-10-07