Techniques to Improve Performance in Requester-Wins Hardware Transactional Memory
Artikel i vetenskaplig tidskrift, 2013

The simplicity of requester-wins Hardware Transactional Memory (HTM) makes it easy to incorporate in existing chip multiprocessors. Hence, such systems are expected to be widely available in the near future. Unfortunately, these implementations are prone to suffer severe performance degradation due to transient and persistent livelock conditions. This article shows that existing techniques are unable to mitigate this degradation effectively. It then proposes and evaluates four novel techniques-two software-based that employ information provided by the hardware and two that require simple core-local hardware additions-which have the potential to boost the performance of requester-wins HTM designs substantially.

hardware transactional memory

requester-wins conflict resolution

Contention management

Författare

A. Armejach

Centro Nacional de Supercomputacion

Ruben Titos Gil

Chalmers, Data- och informationsteknik, Datorteknik

Anurag Negi

Chalmers, Data- och informationsteknik, Datorteknik

O.S. Unsal

Centro Nacional de Supercomputacion

A. Cristal

Centro Nacional de Supercomputacion

Transactions on Architecture and Code Optimization

1544-3566 (ISSN) 1544-3973 (eISSN)

Vol. 10 4 articlenr, 42-

High Performance and Embedded Architecture and Compilation (HiPEAC)

Europeiska kommissionen (FP7), 2012-01-01 -- 2015-12-31.

Ämneskategorier

Datavetenskap (datalogi)

DOI

10.1145/2555289.2555299