An Efficient Twin-Precision Multiplier
Paper i proceeding, 2004

We present a twin-precision multiplier that in normal operation mode efficiently performs N-b multiplications. For applications where the demand on precision is relaxed, the multiplier can perform N/2-b multiplications while expending only a fraction of the energy of a conventional N-b multiplier. For applications with high demands on throughput, the multiplier is capable of performing two independent N/2-b multiplications in parallel. A comparison between two signed 16-b multipliers, where both perform single 8-b multiplications, shows that the twin-precision multiplier has 72% lower power dissipation and 15% higher speed than the conventional one, while only requiring 8% more transistors.

Författare

Magnus Själander

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

Henrik Eriksson

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

Per Larsson-Edefors

Chalmers, Institutionen för datorteknik, Integrerade elektroniksystem

International Conference on Computer Design (ICCD)

30-33

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1109/ICCD.2004.1347894