Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?
Paper i proceeding, 2015

First defined two decades ago, the memory wall remains a fundamental limitation to system performance. Recent innovations in 3D-stacking technology enable DRAM devices with much higher bandwidths than traditional DIMMs. The first such products will soon hit the market, and some of the publicity claims that they will break through the memory wall. Here we summarize our analysis and expectations of how such 3D-stacked DRAMs will affect the memory wall for a set of representative HPC applications. We conclude that although 3D-stacked DRAM is a major technological innovation, it cannot eliminate the memory wall.

Memory wall

Bandwidth

Dram

Latency

Hpc

Hybrid memory cube (hmc)

High bandwidth memory (hbm)

Författare

M. Radulovic

Centro Nacional de Supercomputacion

D. Zivanovic

Centro Nacional de Supercomputacion

D. Ruiz

Centro Nacional de Supercomputacion

B. R. De Supinski

Lawrence Livermore National Laboratory

Sally A McKee

Chalmers, Data- och informationsteknik, Datorteknik

P. Radojkovíc

Centro Nacional de Supercomputacion

E. Ayguad

Centro Nacional de Supercomputacion

ACM International Conference Proceeding Series - Proceedings of the 1st International Symposium on Memory Systems, MEMSYS 2015, Washington, United States, 14-15 August 2015

Vol. 05-08-October-2015 31-36

Ämneskategorier

Data- och informationsvetenskap

DOI

10.1145/2818950.2818955

ISBN

978-1-4503-3604-8

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2018-03-23